sci.electronics.basics Google Group

Re: AC coupled offset and gain problem

jon_slaugh...@hotmail.com (Jon Slaughter) — Sat, 21 Nov 2009 06:47:03 UT

An op amp is a device that attemps to keep it's two inputs at the same
voltage reference. The inputs also do not draw any current.
Hence, your positive side is simply a voltage divider
V+ = Vref*R2/(R1+R2)
But then V- = V+
So the current through 1370 res, lets call it R3, is
I = (Vi - V-)/R3
This current is the same current that is going through the 2100 resistor,

Re: AC coupled offset and gain problem

dbee...@videotron.ca (Douglas Beeson) — Sat, 21 Nov 2009 04:05:16 UT

%2835457%29,new
Thank you, Shaun.
I assume you got the 1.7 by dividing the output DC level (2.55) by the gain
(1.53), giving 1.67. Makes sense.
What is the approach, in general, to these problems? Calculate gain first, then
set offset from Vo=Vi(R1/R1+R2)(Rg/Rf+Rg) ?
When I used the TI calculator I used +1.6 and -1.6 as the full scale and zero

Re: AC coupled offset and gain problem

r...@nomail.com (Shaun) — Sat, 21 Nov 2009 01:14:27 UT

You DC offset is as it should be with those values of resistors, 1.5 volts.
You need to change the values of the resistors to the non - inverting input
of the OP-AMP. It's a simple voltage divider then multiplied by the gain of
1.5. You have 1.0 volts going to the non - inverting input, you need 1.7

Re: How delicate is the output of a CMOS IC?

richgr...@example.net (Rich Grise) — Fri, 20 Nov 2009 21:43:39 UT

...
If you're paranoid, you could put a couple of 1N4148's or 1N914's to
Vdd and ground, "downstream" of your load limiting resistor.
Cheers!
Rich

Re: How delicate is the output of a CMOS IC?

pawi...@invalid.com (pawihte) — Fri, 20 Nov 2009 20:21:57 UT

Yes. That's why I have the series resistor at the output, to
serve double duty as a load current limiter *and* for stability
with capacitive loads (it's a low-speed circuit that I have not
yet constructed or even fully designed).
That /is/ stretching it. I suppose I could make doubly sure by
placing bleed resistors between the several output points and

Re: How delicate is the output of a CMOS IC?

et...@ncf.ca (Michael Black) — Fri, 20 Nov 2009 19:40:59 UT

No, the only way you'll damage it is if you end up loading it down
too much (like a short to ground, or by trying to supply too much current
to a following device), and that's not static related. I suppose maybe
a static discharge to the output might jump from the output to the input
and kill it that way, but that's a stretch.

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AC coupled offset and gain problem

unk...@xnntp (Douglas Beeson) — Fri, 20 Nov 2009 16:47:35 UT

I am having trouble understanding the behavior of a circuit I am using to apply
gain and offset to a triangle wave.
The circuit in question is here:
[link]
My triangle wave output is 4 +/- 1.6 V, and I want 2.55 +/- 2.45 V out of the
gain stage. (0.1 - 5 Vpp)

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How delicate is the output of a CMOS IC?

pawi...@invalid.com (pawihte) — Fri, 20 Nov 2009 15:42:04 UT

Are standard CMOS logic ICs any more susceptible to damage from
external causes than BJT devices via the OUTput terminals? By
external causes, I mean things like ESD or a mild leakage current
from the mains supply.
As an example, suppose an output from a 4000 series logic gate is
intended to drive an external load, but may be left open at

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sci.electronics.basics Google Group

Re: AC coupled offset and gain problem

Re: AC coupled offset and gain problem

Re: AC coupled offset and gain problem

Re: How delicate is the output of a CMOS IC?

Re: How delicate is the output of a CMOS IC?

Re: How delicate is the output of a CMOS IC?

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How delicate is the output of a CMOS IC?

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