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  <id>http://groups.google.com.my/group/sci.electronics.basics</id>
  <title type="text">sci.electronics.basics Google Group</title>
  <subtitle type="text">
  Elementary questions about electronics.
  </subtitle>
  <link href="/group/sci.electronics.basics/feed/atom_v1_0_msgs.xml" rel="self" title="sci.electronics.basics feed"/>
  <updated>2009-11-21T06:47:03Z</updated>
  <generator uri="http://groups.google.com.my" version="1.99">Google Groups</generator>
  <entry>
  <author>
  <name>Jon Slaughter</name>
  <email>jon_slaugh...@hotmail.com</email>
  </author>
  <updated>2009-11-21T06:47:03Z</updated>
  <id>http://groups.google.com.my/group/sci.electronics.basics/browse_thread/thread/f46dfdf31e2361f4/06e508fe2bfd56fe?show_docid=06e508fe2bfd56fe</id>
  <link href="http://groups.google.com.my/group/sci.electronics.basics/browse_thread/thread/f46dfdf31e2361f4/06e508fe2bfd56fe?show_docid=06e508fe2bfd56fe"/>
  <title type="text">Re: AC coupled offset and gain problem</title>
  <summary type="html" xml:space="preserve">
  An op amp is a device that attemps to keep it&#39;s two inputs at the same &lt;br&gt; voltage reference. The inputs also do not draw any current. &lt;br&gt; Hence, your positive side is simply a voltage divider &lt;br&gt; V+ = Vref*R2/(R1+R2) &lt;br&gt; But then V- = V+ &lt;br&gt; So the current through 1370 res, lets call it R3, is &lt;br&gt; I = (Vi - V-)/R3 &lt;br&gt; This current is the same current that is going through the 2100 resistor,
  </summary>
  </entry>
  <entry>
  <author>
  <name>Douglas Beeson</name>
  <email>dbee...@videotron.ca</email>
  </author>
  <updated>2009-11-21T04:05:16Z</updated>
  <id>http://groups.google.com.my/group/sci.electronics.basics/browse_thread/thread/f46dfdf31e2361f4/3def76c5bc62a159?show_docid=3def76c5bc62a159</id>
  <link href="http://groups.google.com.my/group/sci.electronics.basics/browse_thread/thread/f46dfdf31e2361f4/3def76c5bc62a159?show_docid=3def76c5bc62a159"/>
  <title type="text">Re: AC coupled offset and gain problem</title>
  <summary type="html" xml:space="preserve">
  %2835457%29,new &lt;br&gt; Thank you, Shaun. &lt;br&gt; I assume you got the 1.7 by dividing the output DC level (2.55) by the gain &lt;br&gt; (1.53), giving 1.67. Makes sense. &lt;br&gt; What is the approach, in general, to these problems? Calculate gain first, then &lt;br&gt; set offset from Vo=Vi(R1/R1+R2)(Rg/Rf+Rg) ? &lt;br&gt; When I used the TI calculator I used +1.6 and -1.6 as the full scale and zero
  </summary>
  </entry>
  <entry>
  <author>
  <name>Shaun</name>
  <email>r...@nomail.com</email>
  </author>
  <updated>2009-11-21T01:14:27Z</updated>
  <id>http://groups.google.com.my/group/sci.electronics.basics/browse_thread/thread/f46dfdf31e2361f4/6cb8dbd534b790fa?show_docid=6cb8dbd534b790fa</id>
  <link href="http://groups.google.com.my/group/sci.electronics.basics/browse_thread/thread/f46dfdf31e2361f4/6cb8dbd534b790fa?show_docid=6cb8dbd534b790fa"/>
  <title type="text">Re: AC coupled offset and gain problem</title>
  <summary type="html" xml:space="preserve">
  You DC offset is as it should be with those values of resistors, 1.5 volts. &lt;br&gt; You need to change the values of the resistors to the non - inverting input &lt;br&gt; of the OP-AMP. It&#39;s a simple voltage divider then multiplied by the gain of &lt;br&gt; 1.5. You have 1.0 volts going to the non - inverting input, you need 1.7
  </summary>
  </entry>
  <entry>
  <author>
  <name>Rich Grise</name>
  <email>richgr...@example.net</email>
  </author>
  <updated>2009-11-20T21:43:39Z</updated>
  <id>http://groups.google.com.my/group/sci.electronics.basics/browse_thread/thread/3a651bd02166d5c6/a53cb30503de1c89?show_docid=a53cb30503de1c89</id>
  <link href="http://groups.google.com.my/group/sci.electronics.basics/browse_thread/thread/3a651bd02166d5c6/a53cb30503de1c89?show_docid=a53cb30503de1c89"/>
  <title type="text">Re: How delicate is the output of a CMOS IC?</title>
  <summary type="html" xml:space="preserve">
  ... &lt;br&gt; If you&#39;re paranoid, you could put a couple of 1N4148&#39;s or 1N914&#39;s to &lt;br&gt; Vdd and ground, &amp;quot;downstream&amp;quot; of your load limiting resistor. &lt;br&gt; Cheers! &lt;br&gt; Rich
  </summary>
  </entry>
  <entry>
  <author>
  <name>pawihte</name>
  <email>pawi...@invalid.com</email>
  </author>
  <updated>2009-11-20T20:21:57Z</updated>
  <id>http://groups.google.com.my/group/sci.electronics.basics/browse_thread/thread/3a651bd02166d5c6/6ae46b4c0684f561?show_docid=6ae46b4c0684f561</id>
  <link href="http://groups.google.com.my/group/sci.electronics.basics/browse_thread/thread/3a651bd02166d5c6/6ae46b4c0684f561?show_docid=6ae46b4c0684f561"/>
  <title type="text">Re: How delicate is the output of a CMOS IC?</title>
  <summary type="html" xml:space="preserve">
  Yes. That&#39;s why I have the series resistor at the output, to &lt;br&gt; serve double duty as a load current limiter *and* for stability &lt;br&gt; with capacitive loads (it&#39;s a low-speed circuit that I have not &lt;br&gt; yet constructed or even fully designed). &lt;br&gt; That /is/ stretching it. I suppose I could make doubly sure by &lt;br&gt; placing bleed resistors between the several output points and
  </summary>
  </entry>
  <entry>
  <author>
  <name>Michael Black</name>
  <email>et...@ncf.ca</email>
  </author>
  <updated>2009-11-20T19:40:59Z</updated>
  <id>http://groups.google.com.my/group/sci.electronics.basics/browse_thread/thread/3a651bd02166d5c6/bdc7ef1ac5b444e1?show_docid=bdc7ef1ac5b444e1</id>
  <link href="http://groups.google.com.my/group/sci.electronics.basics/browse_thread/thread/3a651bd02166d5c6/bdc7ef1ac5b444e1?show_docid=bdc7ef1ac5b444e1"/>
  <title type="text">Re: How delicate is the output of a CMOS IC?</title>
  <summary type="html" xml:space="preserve">
  No, the only way you&#39;ll damage it is if you end up loading it down &lt;br&gt; too much (like a short to ground, or by trying to supply too much current &lt;br&gt; to a following device), and that&#39;s not static related. I suppose maybe &lt;br&gt; a static discharge to the output might jump from the output to the input &lt;br&gt; and kill it that way, but that&#39;s a stretch.
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  <updated>2009-11-20T17:53:13Z</updated>
  <id>http://groups.google.com.my/group/sci.electronics.basics/browse_thread/thread/2f865b8c268e186c/30d42ae181be7924?show_docid=30d42ae181be7924</id>
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  <updated>2009-11-20T17:12:43Z</updated>
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  <name>Douglas Beeson</name>
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  <updated>2009-11-20T16:47:35Z</updated>
  <id>http://groups.google.com.my/group/sci.electronics.basics/browse_thread/thread/f46dfdf31e2361f4/a4956f1c703335e6?show_docid=a4956f1c703335e6</id>
  <link href="http://groups.google.com.my/group/sci.electronics.basics/browse_thread/thread/f46dfdf31e2361f4/a4956f1c703335e6?show_docid=a4956f1c703335e6"/>
  <title type="text">AC coupled offset and gain problem</title>
  <summary type="html" xml:space="preserve">
  I am having trouble understanding the behavior of a circuit I am using to apply &lt;br&gt; gain and offset to a triangle wave. &lt;br&gt; The circuit in question is here: &lt;br&gt; &lt;a target=&quot;_blank&quot; rel=nofollow href=&quot;http://gallery.me.com/doug.beeson#100069/offset%252Bgain&quot;&gt;[link]&lt;/a&gt; &lt;br&gt; My triangle wave output is 4 +/- 1.6 V, and I want 2.55 +/- 2.45 V out of the &lt;br&gt; gain stage. (0.1 - 5 Vpp)
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  <name>pawihte</name>
  <email>pawi...@invalid.com</email>
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  <updated>2009-11-20T15:42:04Z</updated>
  <id>http://groups.google.com.my/group/sci.electronics.basics/browse_thread/thread/3a651bd02166d5c6/59e1e10149ad09ad?show_docid=59e1e10149ad09ad</id>
  <link href="http://groups.google.com.my/group/sci.electronics.basics/browse_thread/thread/3a651bd02166d5c6/59e1e10149ad09ad?show_docid=59e1e10149ad09ad"/>
  <title type="text">How delicate is the output of a CMOS IC?</title>
  <summary type="html" xml:space="preserve">
  Are standard CMOS logic ICs any more susceptible to damage from &lt;br&gt; external causes than BJT devices via the OUTput terminals? By &lt;br&gt; external causes, I mean things like ESD or a mild leakage current &lt;br&gt; from the mains supply. &lt;br&gt; As an example, suppose an output from a 4000 series logic gate is &lt;br&gt; intended to drive an external load, but may be left open at
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